NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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FTMx_CnSC field descriptions (continued)
Field Description
1
ICRST
FTM counter reset by the selected input capture event.
FTM counter reset is driven by the selected event of the channel (n) in the Input Capture mode.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 FTM counter is not reset when the selected channel (n) input event is detected.
1 FTM counter is reset when the selected channel (n) input event is detected.
0
DMA
DMA Enable
Enables DMA transfers for the channel.
0 Disable DMA transfers.
1 Enable DMA transfers.
39.4.7 Channel (n) Value (FTMx_CnV)
These registers contain the captured FTM counter value for the input modes or the match
value for the output modes.
In Input Capture, Capture Test, and Dual Edge Capture modes, any write to a CnV
register is ignored.
In output modes, writes to the CnV register are done on its write buffer. The CnV register
is updated with its write buffer value according to
Registers updated from write buffers .
If FTMEN = 0, a write to CnSC register resets manually this write coherency mechanism.
Address: Base a 10h (8d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
VAL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CnV field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
VAL Channel Value
Captured FTM counter value of the input modes or the match value for the output modes
39.4.8 Counter Initial Value (FTMx_CNTIN)
The Counter Initial Value register contains the initial value for the FTM counter.
Chapter 39 FlexTimer Module (FTM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 869