NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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synchronizer, one rising edge to the filter output, plus one more to the edge detector. In
other words, CHF is set (4 + 4 × CHnFVAL[3:0]) FTM input clock periods after a valid
edge occurs on the channel input.
The clock for the counter in the channel input filter is the system clock divided by 4.
CHnFVAL[3:0] = 0100
(binary value)
channel (n) input
after the synchronizer
counter
filter output *
FTM input clock divided by 4
Time
* Note: Filter output is delayed one system clock of filter counter logic output.
Figure 39-14. Channel input filter example
The figure below shows the delay through the input filter logic considering each internal
filter element. Note that the input signal is delayed only by the synchronizer and edge
dector logic if the filter is disabled.
FTM input clock
channel (n) input
FTM counter
CHnFVAL[3:0]
filter counter
C(n)V
CHF
1 2 3 4 5 6 7 8 9 10 11 12 13
2
1 2 1
0 12
filter output
synchronizer delay filter counter delay
filter
output
delay
edge
detector
delay
Figure 39-15. Input capture example
39.5.5.2 FTM Counter Reset in Input Capture Mode
If the channel (n) is in input capture mode and CnSC[ICRST = 1], then when the selected
input capture event occurs in the channel (n) input signal, the current value of the FTM
counter is captured into the CnV register, the CHF bit is set, the channel (n) interrupt is
generated (if CHIE = 1) and the FTM counter is reset to the CNTIN register value.
Chapter 39 FlexTimer Module (FTM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 921