NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 633 / 1325

30.4.2 16-bit KERMIT CRC
CRC-16/KERMIT: width=16 poly=0x1021 init=0x0000 refin=true refout=true
xorout=0x0000 check=0x2189
uint32_t checksum16, dataSize;
uint8_t data[] = "123456789";
uint32_t *data32;
// Transport Bytes and Bits for both data write and read
// Bytes transport is because of the CRC_DATA requires MSB write first
// Bits transport is because of the KERMIT algorithm requirement
// No complement for checksum result
CRC_CTRL = CRC_CTRL_TOT(2) | CRC_CTRL_TOTR(2) | CRC_CTRL_FXOR(0) |
CRC_CTRL_TCRC(0) | CRC_CTRL_WAS(0);
// write polynomial register
CRC_GPOLY = 0x1021;
// write pre-computed control register value along with WAS to start checksum computation
CRC_CTRL |= CRC_CTRL_WAS(1);
// write seed (initial checksum)
CRC_DATA = 0;
// deassert WAS by writing pre-computed CRC control register value
CRC_CTRL &= ~CRC_CTRL_WAS(1);
// write data
dataSize = sizeof(data);
// 8-bit reads and writes till source address is aligned 4 bytes */
while ((data) && ((uint32_t)data & 3U))
{
CRC_DATA = *data;
data++;
dataSize--;
}
// use 32-bit reads and writes as long as possible
data32 = (uint32_t *)data;
while (dataSize >= sizeof(uint32_t))
{
CRC_DATA = *data32;
+;
dataSize -= sizeof(uint32_t);
}
data = (uint8_t *)data32;
// 8-bit reads and writes till end of data buffer
while (dataSize)
{
CRC_DATA = *data;
data++;
dataSize--;
}
// due to the transport option TOTR >= 2
// read 16bit checksum result from CRC_DATA[HU:HL]
// otherwise, read checksum from CRC_DATA[LU:LL]
checksum16 = (CRC_DATA & 0xFFFF0000) >> 16;
Chapter 30 Cyclic Redundancy Check (CRC)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 633