NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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MMDVSQ_RCND field descriptions
Field Description
RADICAND Radicand
This is the input radicand for a square root calculation, that is, the input "square" number.
6.5 Functional description
This section details the algorithms, execution times of the MMDVSQ, and the software
interface to the module.
6.5.1 Algorithms
This section provides more details on the integer divide and square root algorithms.
Integer divide including special cases
6.5.1.1.1 Overview
The MMDVSQ module implements a "shift, test, and restore" radix-2 algorithm for
unsigned integer divide operations. When performing a signed divide calculation,
negative input operands are converted into 2’s complement positive numbers first, an
unsigned divide performed, and the sign of the results based on the input operand signs,
namely:
• The sign of the remainder is the same as the sign of the dividend
• The quotient is negated if the signs of the dividend and divisor are different
The hardware implementation processes two bits per machine cycle and includes "early
termination" logic where the execution time is data dependent, based on the magnitude of
the positive dividend. See
Table 6-4 for more execution time details.
6.5.1.1.2 Special case: Overflow
There is a single "special overflow case" affecting signed integer divides. If the dividend
= 0x8000_0000 and the divisor = 0xFFFF_FFFF, the result of this (-2
31
/-1) operation
cannot be expressed as a 32-bit 2’s complement number. For this case, the MMDVSQ
exactly follows the ARM Cortex-Mx definition and returns 0x8000_0000 (the lower 32
bits of the +2
31
result) as the quotient with no indication of the overflow condition. If the
remainder is selected as the output of this calculation, it returns 0x0000_0000.
6.5.1.1
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
90 NXP Semiconductors