NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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39.5.8 Center-Aligned PWM (CPWM) mode
The Center-Aligned mode is selected when:
• QUADEN = 0
• DECAPEN = 0
• COMBINE = 0, and
• CPWMS = 1
The CPWM pulse width (duty cycle) is determined by 2 × (CnV − CNTIN) and the
period is determined by 2 × (MOD − CNTIN). See the following figure. MOD must be
kept in the range of 0x0001 to 0x7FFF because values outside this range can produce
ambiguous results.
In the CPWM mode, the FTM counter counts up until it reaches MOD and then counts
down until it reaches CNTIN.
The CHF bit is set and channel (n) interrupt is generated (if CHIE = 1) at the channel (n)
match (FTM counter = CnV) when the FTM counting is down (at the begin of the pulse
width) and when the FTM counting is up (at the end of the pulse width).
This type of PWM signal is called center-aligned because the pulse width centers for all
channels are aligned with the value of CNTIN.
The other channel modes are not compatible with the up-down counter (CPWMS = 1).
Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1).
pulse width
counter overflow
FTM counter =
MOD
period
2 x (CnV - CNTIN)
2 x (MOD - CNTINCNTIN)
FTM counter = CNTIN
channel (n) match
(FTM counting
is down)
channel (n) match
(FTM counting
is up)
counter overflow
FTM counter =
MOD
channel (n) output
Figure 39-23. CPWM period and pulse width with ELSB:ELSA = 1:0
If (ELSB:ELSA = 0:0) when the FTM counter reaches the value in the CnV register, the
CHF bit is set and the channel (n) interrupt is generated (if CHIE = 1), however the
channel (n) output is not controlled by FTM.
If (ELSB:ELSA = 1:0), then the channel (n) output is forced high at the channel (n)
match (FTM counter = CnV) when counting down, and it is forced low at the channel (n)
match when counting up. See the following figure.
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
926 NXP Semiconductors