NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Operation in Run mode, module functionality for bus masters and slaves is the equivalent
of STOP mode. When enabling Compute Operation in VLPR mode, module functionality
for bus masters and slaves is the equivalent of VLPS mode. SCG, PMC, SRAM and
Flash read port are not affected by Compute Operation, although the Flash register
interface is disabled.
During Compute Operation, the AIPS peripheral space is disabled and attempted accesses
generate bus errors. The private peripheral bus (PPB) remains accessible during Compute
Operation, including the MCM, System Control Space (SCS) (for NVIC), and SysTick.
Although access to the GPIO registers is supported, the GPIO port data input registers do
not return valid data since clocks are disabled to the Port Control and Interrupt modules.
By writing to the GPIO port data output registers, it is possible to control those GPIO
ports that are configured as output pins.
Compute Operation is controlled by the CPO register in the MCM, which is only
accessible to the CPU. Setting or clearing the CPOREQ bit in the MCM initiates entry or
exit into Compute Operation. Compute Operation can also be configured to exit
automatically on detection of an interrupt, which is required in order to service most
interrupts. Only the core system interrupts (exceptions, including NMI and SysTick) and
any edge sensitive interrupts can be serviced without exiting Compute Operation.
When entering Compute Operation, the CPOACK status bit indicates when entry has
completed. When exiting Compute Operation in Run mode, the CPOACK status bit
negates immediately. When exiting Compute Operation in VLPR mode, the exit is
delayed to allow the PMC to handle the change in power consumption. This delay means
the CPOACK bit is polled to determine when the AIPS peripheral space can be accessed
without generating a bus error.
The DMA wakeup is also supported during Compute Operation and causes the CPOACK
status bit to clear and the AIPS peripheral space to be accessible for the duration of the
DMA wakeup. At the completion of the DMA wakeup, the device transitions back into
Compute Operation.
24.2.2 Wait mode
Wait mode refers to a power modes in which the CPU execution is halted. The core clock
is gated off. The system clock continues to operate. Bus clocks, if enabled, continue to
operate.
Depending on the on-chip regulator settings, Wait mode has the following configurations:
Power Modes Description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
550 NXP Semiconductors