NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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PMC_LVDSC1 field descriptions (continued)
Field Description
This bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling)
1 Request a hardware interrupt when LVDF = 1
4
LVDRE
Low Voltage Detect Reset Enable
This bit enables the low voltage detect events to generate a system reset.
0 No system resets on low voltage detect events.
1 If the supply voltage falls below V
LVD
, a system reset will be generated.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
26.6.2 Low Voltage Detect Status and Control 2 Register
(PMC_LVDSC2)
This register contains status and control bits to support the low voltage warning (LVW)
function.
NOTE
When the internal voltage regulator is in low power mode, the
LVD system is disabled regardless of the PMC_LVDSC2
settings.
Address: 4007_D000h base + 1h offset = 4007_D001h
Bit 7 6 5 4 3 2 1 0
Read LVWF
LVWIE
0
Write LVWACK
Reset 0 0 0 0 0 0 0 0
PMC_LVDSC2 field descriptions
Field Description
7
LVWF
Low-Voltage Warning Flag
This bit read-only status bit indicates a low-voltage detect event. The threshold voltage is V
LVW
.
0 Low-voltage warning event not detected
1 Low-voltage warning event detected
6
LVWACK
Low-Voltage Warning Acknowledge
This write-only bit is used to acknowledge low voltage warning errors. Write 1 to clear LVWF. Reads
always return 0.
Table continues on the next page...
Chapter 26 Power Management Controller (PMC)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 585