NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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When a rising edge occurs in the channel (n) input signal, the FTM counter value is
captured into channel (n) capture buffer. The channel (n) capture buffer value is
transferred to C(n)V register when a falling edge occurs in the channel (n) input signal.
C(n)V register has the FTM counter value when the previous rising edge occurred, and
the channel (n) capture buffer has the FTM counter value when the last rising edge
occurred.
When a falling edge occurs in the channel (n) input signal, the FTM counter value is
captured into channel (n+1) capture buffer. The channel (n+1) capture buffer value is
transferred to C(n+1)V register when the C(n)V register is read.
In the following figure, the read of C(n)V returns the FTM counter value when the event
1 occurred and the read of C(n+1)V returns the FTM counter value when the event 2
occurred.
read C(n+1)V
FTM counter
channel (n) input
(after the filter
channel input)
channel (n)
capture buffer
C(n)V
C(n+1)V
channel (n+1)
capture buffer
event 1 event 2 event 3 event 4 event 5 event 6 event 7 event 8 event 9
1 2 3 4 5 6 7 8 9
9
1 3 7 5
6 8 4 2
2
1 3 5 7
read C(n)V
Figure 39-92. Dual Edge Capture mode read coherency mechanism
C(n)V register must be read prior to C(n+1)V register in dual edge capture one-shot and
continuous modes for the read coherency mechanism works properly.
39.5.27 Quadrature Decoder mode
The Quadrature Decoder mode is selected if (QUADEN = 1). The Quadrature Decoder
mode uses the input signals phase A and B to control the FTM counter increment and
decrement. The following figure shows the quadrature decoder block diagram.
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
980 NXP Semiconductors