NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 105 / 1325

Chapter 8
Bit Manipulation Engine (BME)
8.1 Chip-specific Information for this Module
In this block chapter, PBRIDGE stands for the Peripheral Bridge, with the same meaning
as AIPS-Lite.
8.2 Introduction
The Bit Manipulation Engine (BME) provides hardware support for atomic read-modify-
write memory operations to the peripheral address space in Cortex-M0+ based
microcontrollers.
This architectural capability is also known as "decorated storage" as it defines a
mechanism for providing additional semantics for load and store operations to memory-
mapped peripherals beyond just the reading and writing of data values to the addressed
memory locations. In the BME definition, the "decoration", that is, the additional
semantic information, is encoded into the peripheral address used to reference the
memory.
By combining the basic load and store instructions of the Arm Cortex-M instruction set
architecture (v6M, v7M) with the concept of decorated storage provided by the BME, the
resulting implementation provides a robust and efficient read-modify-write capability to
this class of ultra low-end microcontrollers. The resulting architectural capability defined
by this core platform function is targeted at the manipulation of n-bit fields in peripheral
registers and is consistent with I/O hardware addressing in the Embedded C standard. For
most BME commands, a single core read or write bus cycle is converted into an atomic
read-modify-write, that is, an indivisible "read followed by a write" bus sequence.
BME decorated references are only available on system bus transactions generated by the
processor core and targeted at the standard 512 KB peripheral address space based at
0x4000_0000
1
. The decoration semantic is embedded into address bits[28:19], creating a
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 105