NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Table 47-12. I2S Slave Configuration
Register Value Comments
SHIFTCFGn 0x0000_0000 Start and stop bit disabled.
SHIFTCTLn 0x0103_0002 Configure transmit using Timer 1 on
rising edge of shift clock with output data
on Pin 0.
SHIFTCFG(n+1) 0x0000_0000 Start and stop bit disabled.
SHIFTCTL(n+1) 0x0180_0101 Configure receive using Timer 1 on
falling edge of shift clock with input data
on Pin 1.
TIMCMPn 0x0000_007D Configure two 32-bit transfers per frame.
Set TIMCMP[15:0] = (number of bits x 4)
- 3.
TIMCFGn 0x0030_2400 Configure enable on pin rising edge
(inverted frame sync) and disable on
compare, initial clock state is logic 1 and
decrement on trigger input (bit clock).
TIMCTLn 0x0440_0383 Configure 16-bit counter using inverted
Pin 3 input (frame sync), with Pin 2 input
(bit clock) as the trigger.
TIMCMP(n+1) 0x0000_003F Configure 32-bit transfers. Set
TIMCMP[15:0] = (number of bits x 2) - 1.
TIMCFG(n+1) 0x0020_3500 Configure enable on pin rising edge with
trigger high and disable on compare with
trigger low, initial clock state is logic 0
and decrement on pin input.
TIMCTL(n+1) 0x0340_0203 Configure 16-bit counter using Pin 2
input (bit clock), with Timer 0 output as
the trigger.
SHIFTBUFn Data to transmit Transmit data can be written to
SHIFTBUFBIS, use the Shifter Status
Flag to indicate when data can be
written using interrupt or DMA request.
Can support LSB first transfer by writing
to SHIFTBUF register instead.
SHIFTBUF(n+1) Data to receive Received data can be read from
SHIFTBUFBIS, use the Shifter Status
Flag to indicate when data can be read
using interrupt or DMA request. Can
support LSB first transfer by reading
from SHIFTBUF register instead.
47.6 Usage Guide
UART Transmit
Chapter 47 Flexible I/O (FlexIO)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1261