NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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typical run-control scenarios. The status register bits also provide a means for the
debugger to get updated status of the core without having to initiate a bus transaction
across the crossbar switch, thus remaining less intrusive during a debug session.
A miscellaneous debug module (MDM) is implemented on this device, which contains
the DAP control and status registers. It is important to note that these DAP control and
status registers are not memory-mapped within the system memory map and are only
accessible via the Debug Access Port using SWD. The MDM-AP is accessible as Debug
Access Port 1 with the available registers shown in the table below.
Table 31-2. MDM-AP register summary
Address Register Description
0x0100_0000 Status See MDM-AP status register
0x0100_0004 Control See MDM-AP Control register
0x0100_00FC IDR Read-only identification register that
always reads as 0x001C_0020
SWD status and control registers
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
636 NXP Semiconductors