NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1042 / 1325

The PWT counter uses the frequency divided clock from CLKPRE for counter
advancing. The frequency of pre-scaler is programmable as the clock frequency divided
by 1, 2, 4, 8, 16, 32, 64, 128 (depending on the setting of PRE[2:0]).
When PWT_CNT is running, any edge to be measured after the trigger edge causes the
value of the PWT_CNT to be uploaded to the appropriate pulse width registers. At the
same time, PWT_CNT will be reset to $0000 and the clock pre-scaler output will also be
reset together. PWT_CNT will then start advancing again with the input clock. If the
PWTxCNT runs from 0xFFFF to 0x0000, the PWTOV bit is set.
41.5.2 Edge detection and capture control
The edge detection and capture control part detects measurement trigger edges and
controls when and which pulse width register(s) will be updated.
The edge detection logic determines from which edge appeared on PWTIN the pulse
width starts to be measured, when and which pulse width registers should be updated.
The PWTIN can be selected from one of four sources by configuring PINSEL[1:0].
As soon as the PWT is enabled, the 16-bit free counter will begin to count up until a edge
transistion on the selected PWTIN. Determined by PWT_CS[FCTLE] and PWTIN state,
the counter contents can be uploaded to the corresponding registers.
If PWT_CS[FCTLE] is cleared to 0, the first 16-bit free counter content will just be
ignored and not uploaded to neither PWT_PPH:L nor PWT_NPH:L. Otherwise,
detemined by current PWTIN state(as signalized by PWT_CR[LVL]), the counter
content will be uploaded to PWT_PPH:L if PWT_CR[LVL] is 1 and PWT_NPH:L if
PWT_CR[LVL] is 0.
In normal measurement, when the PWT_CS[PWTRDY] is set, software can then read out
the positive pulse width and negative pulse width values from PWT_PPH:L and
PWT_NPH:L respectively and the selected PWTIN duty ratio can then be calculated. The
exception is when overflow happens, software need to check PWT_CR[TGL] and
PWT_CR[LVL] to determine if it is low overflow(0 duty ratio) ,high overflow(100%
duty ratio), toggled low overflow or toggled high overflow. Below table 1 shows the
meaning:
Table 41-3. Abnormal PWTIN duty ratio
Flag PWT_CR[ TGL] PWT_CR[ LVL] Description
PWT_CS[ PWTOV] 0 0 Low overflow
0 1 High overflow
1 0 Toggled low overflow
Table continues on the next page...
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1042 NXP Semiconductors