NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Table 44-3. LPSPI Command Word (continued)
Field Description Modify During Transfer
CONT Configures for a continuous transfer that
keeps PCS asserted between frames
(as configured by FRAMESZ). A new
command word is required to cause
PCS to negate. Also supports changing
the command word at frame size
boundaries.
Y
CONTC Indicates this is a new command word
for the existing continuous transfer. This
bit is ignored when not written to the
transmit/command FIFO on a frame
boundary.
Y
RXMSK Masks the receive data and does not
store to the receive FIFO or perform
receive data matching. Useful for half-
duplex transfers or to configure which
fields are compared during receive data
matching.
Y
TXMSK Masks the transmit data, so that data is
not pulled from transmit FIFO and the
output data pin is tristated (unless
configured by OUTCFG). Useful for half-
duplex transfers.
Y
WIDTH Configures the number of bits shifted on
each LPSPI_SCK pulse. Single bit
transfers support traditional SPI bus
transfers in either half-duplex or full-
duplex data formats. Two and four bit
transfers are useful for interfacing to
QuadSPI memory devices and only
support half-duplex data formats (at
least one of TXMSK or RXMSK must
also be set).
Y
FRAMESZ Configures the number of bits in each
frame to 1. The minimum
frame size is 8-bits and the maximum
frame size is 4096-bits. If the frame size
is less than or equal to 32-bits, the word
size and frame size are identical. If the
frame size is greater than 32-bits, then
the word size is 32-bits for each word
except the last (the last word contains
the remainder bits if the frame size is not
divisible by 32). The minimum word size
is 2-bits, a frame size of 33-bits (or
similar) is not supported.
Y
The LPSPI initiates a SPI bus transfer when data is written to the transmit FIFO, the
HREQ pin is asserted (or disabled) and the LPSPI is enabled. The SPI bus transfer uses
the attributes configured in the transmit command register and timing parameters from
the clock configuration register to perform the transfer. The SPI bus transfer ends once
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1116 NXP Semiconductors