NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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• It can be a free-running counter or a counter with initial and final value
• The counting can be up or up-down
• Each channel can be configured for input capture, output compare, or edge-aligned
PWM mode
• In Input Capture mode:
• The capture can occur on rising edges, falling edges or both edges
• An input filter can be selected for some channels.
• In Output Compare mode the output signal can be set, cleared, or toggled on match
• All channels can be configured for center-aligned PWM mode
• Each pair of channels can be combined to generate a PWM signal with independent
control of both edges of PWM signal
• The FTM channels can operate as pairs with equal outputs, pairs with
complementary outputs, or independent channels with independent outputs
• The deadtime insertion is available for each complementary pair
• Generation of match triggers
• Software control of PWM outputs
• Up to 4 fault inputs for global fault control
• The polarity of each channel is configurable
• The generation of an interrupt per channel
• The generation of an interrupt when the counter overflows
• The generation of an interrupt when the fault condition is detected
• The generation of an interrupt when a register reload point occurs
• Synchronized loading of write buffered FTM registers
• Half cycle and Full cycle register reload capacity
• Write protection for critical registers
• Backwards compatible with TPM
• Testing of input capture mode
• Direct access to input pin states
Introduction
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
852 NXP Semiconductors