NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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PMC_REGSC field descriptions (continued)
Field Description
2
REGFPM
Regulator in Full Performance Mode Status Bit
This read-only bit provides the current status of the internal voltage regulator.
0 Regulator is in low power mode or transition to/from
1 Regulator is in full performance mode
1
CLKBIASDIS
Clock Bias Disable Bit
This bit disables the bias currents and reference voltages for some clock modules in order to further
reduce power consumption in STOP or VLPS mode if all clocks are disabled. The bias currents and
reference voltages for LPFLL (if available on device) are always disabled in LPM.
Note: Using this bit it must be ensured that respective clock modules are disabled in STOP or
VLPS mode. Else severe malfunction of clock modules will happen.
0 No effect
1 In STOP or VLPS mode the bias currents and reference voltages for the following clock modules are
disabled: SIRC, FIRC, PLL. (if available on device)
0
BIASEN
Bias Enable Bit
This bit enables source and well biasing for the core logic in low power mode. In full performance mode
this bit has no effect. This is useful to further reduce MCU power consumption in low power mode.
0 Biasing disabled, core logic can run in full performance
1 Biasing enabled, core logic is slower and there are restrictions in allowed system clock speed (see
Data Sheet for details)
26.6.4 Low Power Oscillator Trim Register (PMC_LPOTRIM)
This register contains the period trimming bits for the low power oscillator.
Table 26-1. Trimming effect of LPOTRIM[4:0]
LPOTRIM[4:0] Decimal Period of LPO clock
10000 –16 lowest
10001 –15 increasing
... ...
11110 –2
11111 –1
00000 0 typical 128 kHz
00001 +1 increasing
... ...
01110 +14
01111 +15 highest
Chapter 26 Power Management Controller (PMC)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 587