NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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18.2 Introduction
The system clock generator (SCG) module provides the system clocks of the MCU. The
SCG contains a frequency-locked loop (LPFLL), a slow internal reference clock (SIRC),
a fast internal reference clock (FIRC), and the system oscillator clock (SOSC). The
LPFLL trimming is controlled by the either the SOSC reference clock, SIRC reference
clock or FIRC reference clock. The SCG can select either the output clock of the LPFLL,
or a SCG reference clock (SIRC, FIRC, and SOSC) as the source for the MCU system
clocks. The SCG also supports operation with crystal oscillators, which allows an
external crystal, ceramic resonator, or another external clock source to produce the
external reference clock (which are also available as clock sources for the MCU systems
clocks).
18.2.1 Features
Key features of the SCG module are:
• Low Power Frequency Locked-Loop (LPFLL):
• Programmable multiplier for up to 4 different frequency ranges
• Internal reference clocks or oscillators reference clocks can be used as the
LPFLL source for trimming purposes
• Can be selected as the clock source for the MCU system clocks
• 3 programmable post-divider clock outputs, which can be used as a clock source
for other on-chip peripherals
• 2 Internal reference clock (IRC) generators:
• Fast IRC clock with programmable High and Low frequency range
• Either the slow or the fast clock can be selected as the clock source for the MCU
system clocks
• 2 programmable post-divider clock outputs for each IRC, which can be used as
clock sources for other on-chip peripherals
• System Crystal Oscillator:
Introduction
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
372 NXP Semiconductors