NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1248 / 1325

The Timer Configuration Register (TIMCFGn) should be configured before setting the
Timer Mode (TIMOD). Once the TIMOD is configured for the desired mode, when the
condition configured by timer enable (TIMENA) is detected then the following events
occur.
• Timer counter will load the current value of the Compare Register and start
decrementing as configured by TIMDEC.
• Timer output will set depending on the TIMOUT configuration.
• Transmit shifters controlled by this timer will either output their start bit value, or
load the shift register from the shift buffer and output the first bit, as configured by
SSTART.
The Timer will then generate the timer output and timer shift clock depending on the
TIMOD and TIMDEC fields. The shifter clock is either equal to the timer output (when
TIMDEC=00 or 01) or equal to the decrement clock (when TIMDEC=10 or 11). When
TIMDEC is configured to decrement from a pin or trigger, the timer will decrement on
both rising and falling edges.
When the Timer is configured to reset as configured in the TIMRST field then the Timer
counter will load the current value of the Compare Register again, the timer output may
also be affected by the reset as configured in TIMOUT.
If the Timer start bit is enabled, the timer counter will reload with the compare register on
the first rising edge of the shift clock after the timer starts decrementing. If there is no
falling edge on the shift clock before the first rising edge (for example, when
TIMOUT=1), a shifter that is configured to shift on falling edge and load on the first shift
will not load correctly.
When configured for 8-bit counter mode, whenever the lower 8-bit counter decrements to
zero the timer output will toggle, the lower 8-bit counter register will reload from the
compare register and the upper 8-bit counter will decrement. For 8-bit PWM mode, the
lower 8-bit counter will only decrement when the output is high and the upper 8-bit
counter will only decrement when the output is low. The timer output will toggle
whenever either lower or upper 8-bit counter decrements to zero.
When the timer decrements to zero, a compare event occurs depending on the timer
mode. For 8-bit counter or PWM modes, both halves of the counter must equal zero and
the upper half must decrement for the timer compare event to occur, while in 16-bit mode
the entire counter must equal zero and decrement. The timer compare event will cause the
timer status flag to set, the timer counter to load the contents of the timer compare
register, the timer output to toggle, any configured transmit shift registers to load and any
configured receive shift registers to store .
When the is Timer is configured to add a stop bit on each compare, the following
additional events will occur.
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1248 NXP Semiconductors