NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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34.1.3 Application-related Information
1. A given peripheral function must be assigned to a maximum of one package pin. Do
not program the same function to more than one pin.
2. To ensure the best signal timing for a given peripheral's interface, choose the pins in
closest proximity to each other.
3. The clock to the port control module can be gated on and off using the PCC_PORTx
register. These bits are cleared after any reset, which disables the clock to the
corresponding module to conserve power. Prior to initializing the corresponding
module, set PCC_PORTx[CGC] to enable the clock. Before turning off the clock,
make sure to disable the module. For more details, refer to
the clock distribution
chapter .
34.2 Introduction
34.3 Overview
The Port Control and Interrupt (PORT) module provides support for port control, digital
filtering, and external interrupt functions.
Most functions can be configured independently for each pin in the 32-bit port and affect
the pin regardless of its pin muxing state.
There is one instance of the PORT module for each port. Not all pins within each port are
implemented on a specific device.
34.3.1 Features
The PORT module has the following features:
• Pin interrupt
• Interrupt flag and enable registers for each pin
• Support for edge sensitive (rising, falling, both) or level sensitive (low, high)
configured per pin
• Support for interrupt or DMA request configured per pin
• Asynchronous wake-up in low-power modes
• Pin interrupt is functional in all digital pin muxing modes
• Digital input filter
• Digital input filter for each pin, usable by any digital peripheral muxed onto the
pin
• Individual enable or bypass control field per pin
Chapter 34 Port Control and Interrupts (PORT)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 693