NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 357 / 1325

Chapter 17
Clock Distribution
17.1 Introduction
This chapter presents the clock architecture overview of this device, the clock distribution
and module clocks, and a clock terminology section. The clocking generation and
configuration can be divided into 3 parts:
1. Clock sources generation
• FIRC, SIRC, SOSC, LPFLL, all from the SCG module
• OSC32
• LPO from PMC
2. Peripheral Clock Controller (PCC)
3. Module level clock control (Inside specific peripherals)
The System Clock Generator (SCG) module is used on this device for main system clock
generation. It generates clock sources like Fast IRC (FIRC, 48/52/56/60M, within 1%
accuracy), Slow IRC (SIRC, 2/8M, within 3% accuracy), System Oscillator (SOSC) and
LPFLL. It controls which clock source is used to derive the system clocks. The SCG also
divides the selected clock source into a variety of clock domains, including the clocks for
the system bus masters, system bus slaves, and flash memory .
Besides the clocks generated by SCG, there are other clock generator: OSC32, LPO from
PMC.
Clock selection for most modules is controlled by the Peripheral Clock Controller (PCC)
module. The PCC also implements module-specific clock gating to allow granular shutoff
of modules.
Various modules have module-specific clocks that can be generated from the
FIRC_CLK, SIRC_CLK, SOSC_CLK, FLL_CLK clock. In addition, there are various
other module-specific clocks that have other alternate sources. While clock selection for
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 357