NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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45.4.1.3 Bus clock
The bus clock is only used for bus accesses to the control and configuration registers. The
bus clock frequency must be sufficient to support the data bandwidth requirements of the
LPI2C master and slave registers.
45.4.1.4 Chip reset
The logic and registers for the LPI2C master and slave are reset to their default state on a
chip reset.
45.4.1.5 Software reset
The LPI2C master implements a software reset bit in its Control Register. The
MCR[RST] will reset all master logic and registers to their default state, except for the
MCR itself.
The LPI2C slave implements a software reset bit in its Control Register. The SCR[RST]
will reset all slave logic and registers to their default state, except for the SCR itself.
45.4.1.6 FIFO reset
The LPI2C master implements write-only control bits that resets the transmit FIFO
(MCR[RTF] and receive FIFO (MCR[RRF]). A FIFO is empty after being reset.
The LPI2C slave implements write-only control bits that resets the transmit data register
(SCR[RTF] and receive data register (SCR[RRF]). A data register is empty after being
reset.
45.4.2 Master Mode
The LPI2C master logic operates independently from the slave logic to perform all
master mode transfers on the I2C bus.
45.4.2.1 Transmit and Command FIFO
The transmit FIFO stores command data to initiate the various I2C operations. The
following operations can be initiated through commands in the transmit FIFO:
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1162 NXP Semiconductors