NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 764 / 1325

• ALTCLKx: As defined for this MCU. See the chip configuration information.
Conversions are possible using ALTCLKx as the input clock source while the MCU
is in Normal Stop mode. ALTCLK1 is the default selection following reset.
Whichever clock is selected, its frequency must fall within the specified frequency range
for ADCK. If the available clocks are too slow, the ADC may not perform according to
specifications. If the available clocks are too fast, the clock must be divided to the
appropriate frequency. This divider is specified by CFG1[ADIV] and can be divide-by 1,
2, 4, or 8. The ADC bus clock frequency must be greater than or equal to the ADC ALT
clock frequency. Please refer to the device datasheet for the ADC specifications.
36.5.2 Voltage reference selection
The ADC can be configured to accept one of the two voltage reference pairs as the
reference voltage (V
REFSH
and V
REFSL
) used for conversions.
Each pair contains a positive reference that must be between the minimum Ref Voltage
High and V
DDA
, and a ground reference that must be at the same potential as V
SSA
. The
two pairs are external (V
REFH
and V
REFL
) and alternate (V
ALTH
). These voltage
references are selected using SC2[REFSEL]. The alternate V
ALTH
voltage reference may
select additional external pin or internal source depending on MCU configuration. See
the chip configuration information for the voltage references specific to this MCU.
36.5.3 Hardware trigger and channel selects
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT,
that is enabled when SC2[ADTRG] is set and a hardware trigger select event,
ADHWTSn, has occurred.
This source is not available on all MCUs. See the chip-specific ADC information for
information on the ADHWT source and the ADHWTSn configurations specific to this
MCU.
When an ADHWT source is available and hardware trigger is enabled, that is
SC2[ADTRG]=1, a conversion is initiated on the rising edge of ADHWT after a
hardware trigger select event, ADHWTSn, has occurred. If a conversion is in progress
when a rising edge of a trigger occurs, the rising edge is ignored. In continuous
conversionn configuration, only the initial rising edge to launch continuous conversions
is observed, and until conversion is aborted, the ADC continues to do conversions on the
same SCn register that initiated the conversion. The hardware trigger function operates in
conjunction with any of the conversion modes and configurations.
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
764 NXP Semiconductors