NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1128 / 1325

Table 45-2. Chip modes supported by the LPI2C module
Chip mode LPI2C Operation
Run Normal operation
Stop/Wait Can continue operating provided the Doze Enable bit (MCR[DOZEN]) is set and
the LPI2C is using an external or internal clock source which remains operating
during stop/wait modes.
Debug Can continue operating provided the Debug Enable bit (MCR[DBGE]) is set.
45.2.5 Signal Descriptions
Signal Description I/O
SCL LPI2C clock line. In 4-wire mode, this is
the SCL input pin. I/O
SDA LPI2C data line. In 4-wire mode, this is
the SDA input pin. I/O
HREQ Host request, can initiate an LPI2C
master transfer if asserted and the I2C
bus is idle. I
SCLS Secondary I2C clock line. In 4-wire
mode, this is the SCL output pin. If
LPI2C master/slave are configured to
use separate pins, this the LPI2C slave
SCL pin. I/O
SDAS Secondary I2C data line. In 4-wire mode,
this is the SDA output pin. If LPI2C
master/slave are configured to use
separate pins, this the LPI2C slave SDA
pin. I/O
Memory Map and Registers
LPI2C memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_6000 Version ID Register (LPI2C0_VERID) 32 R See section 45.3.1/1131
4006_6004 Parameter Register (LPI2C0_PARAM) 32 R See section 45.3.2/1131
4006_6010 Master Control Register (LPI2C0_MCR) 32 R/W 0000_0000h 45.3.3/1132
4006_6014 Master Status Register (LPI2C0_MSR) 32 R/W 0000_0001h 45.3.4/1133
4006_6018 Master Interrupt Enable Register (LPI2C0_MIER) 32 R/W 0000_0000h 45.3.5/1135
4006_601C Master DMA Enable Register (LPI2C0_MDER) 32 R/W 0000_0000h 45.3.6/1137
Table continues on the next page...
45.3
Memory Map and Registers
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1128 NXP Semiconductors