NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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• PDB Channel n Delay m register (CHnDLYm)
• PDB Pulse-Out y Delay register (POyDLY)
The internal registers of them are buffered and any values written to them are written first
to their buffers. The circumstances that cause their internal registers to be updated with
the values from the buffers are summarized in the next table.
Table 38-5. When delay registers are updated
SC[LDMOD] Update to the delay registers
00 The internal registers are loaded with the values from their buffers
immediately after 1 is written to SC[LDOK].
01 The PDB counter reaches PDB_MOD[MOD] + 1 value, after 1 is
written to SC[LDOK].
10 A trigger input event is detected after 1 is written to SC[LDOK].
11 Either the PDB counter reaches PDB_MOD[MOD] + 1 value or a
trigger input event is detected, after 1 is written to SC[LDOK].
After 1 is written to SC[LDOK], the buffers cannot be written until the values in buffers
are loaded into their internal registers. SC[LDOK] is self-cleared when the internal
registers are loaded, so the application code can read it to determine the updates to the
internal registers.
The following diagrams show the cases of the internal registers being updated with
SC[LDMOD] is 00 and x1.
PDB counter
Ch n pre-trigger 0
Ch n pre-trigger 1
CH n DLY1
CH n DLY0
SC[LDOK]
Figure 38-4. Registers update with SC[LDMOD] = 00
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
842 NXP Semiconductors