NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1106 / 1325

LPSPIx_DMR1 field descriptions (continued)
Field Description
Compared against the received data when receive data match is enabled.
44.3.11 Clock Configuration Register (LPSPIx_CCR)
The CCR is only used in master mode and cannot be changed when the LPSPI is enabled.
Address: Base a 40h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SCKPCS PCSSCK DBT SCKDIV
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPSPIx_CCR field descriptions
Field Description
31–24
SCKPCS
SCK to PCS Delay
Configures the delay in master mode from the last SCK edge to the PCS negation. The delay is equal to
( 1) cycles of the LPSPI functional clock divided by the PRESCALE configuration, and the
minimum delay is 1 cycle.
23–16
PCSSCK
PCS to SCK Delay
Configures the delay in master mode from the PCS assertion to the first SCK edge. The delay is equal to
( 1) cycles of the LPSPI functional clock divided by the PRESCALE configuration, and the
minimum delay is 1 cycle.
15–8
DBT
Delay Between Transfers
Configures the delay in master mode from the PCS negation to the next PCS assertion. The delay is equal
to (DBT + 2) cycles of the LPSPI functional clock divided by the PRESCALE configuration, and the
minimum delay is 2 cycles. Note that half the delay occurs before PCS assertion and the other half of the
delay occurs after PCS negation; the full command word can only update in the middle.
Also configures the delay in master mode from the last SCK edge of a transfer word and the first SCK
edge of the next transfer word in a continuous transfer. The delay is equal to (DBT + 1) cycles of the
LPSPI functional clock divided by the PRESCALE configuration, and the minimum delay is 1 cycle.
SCKDIV SCK Divider
Configures the divide ratio of the SCK pin in master mode. The SCK period is equal to (2) cycles
of the LPSPI functional clock divided by the PRESCALE configuration, and the minimum period is 2
cycles. If the period is an odd number of cycles, then the first half of the period will be one cycle longer
than the second half of the period.
Memory Map and Registers
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1106 NXP Semiconductors