NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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PWT_CS field descriptions (continued)
Field Description
1
PWTRDY
PWT Pulse Width Valid
Indicates that the PWT Pulse Width register(s) has been updated and is ready to be read. This field is
cleared by reading PWTRDY and then writing 0 to PWTRDY bit when PWTRDY is set.Writing 1 to this
field has no effect.
0 PWT pulse width register(s) is not up-to-date.
1 PWT pulse width register(s) has been updated.
0
PWTOV
PWT Counter Overflow
Indicates that the PWT counter has run from 0x0000_0xFFFF to 0x0000_0x0000. This field is cleared by
writing 0 to PWTOV when PWTOV is set. Writing 1 to this field has no effect. If another overflow occurs
when this field is being cleared, the clearing fails.
0 PWT counter no overflow.
1 PWT counter runs from 0xFFFF to 0x0000.
41.4.2 Pulse Width Timer Control Register (PWT_CR)
Address: 4005_6000h base + 1h offset = 4005_6001h
Bit 7 6 5 4 3 2 1 0
Read
PCLKS PINSEL
TGL LVL
PRE
Write w1c
Reset
0 0 0 0 0 0 0 0
PWT_CR field descriptions
Field Description
7
PCLKS
PWT Clock Source Selection
Controls the selection of clock source for the PWT counter.
0 BUS_CLK is selected as the clock source of PWT counter.
1 Alternative clock is selected as the clock source of PWT counter.
6–5
PINSEL
PWT Pulse Inputs Selection
Enables the corresponding PWT input port, if this PWT input comes from an external source.
00 PWTIN[0] is enabled.
01 PWTIN[1] is enabled.
10 PWTIN[2] enabled.
11 PWTIN[3] enabled.
4
TGL
PWTIN states Toggled from last state
This flag indicates if the selected PWTIN has toggled its state since last time this bit has cleared to 0.
Table continues on the next page...
Memory Map and Register Descriptions
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1038 NXP Semiconductors