NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Address: 4007_E000h base + 10h offset = 4007_E010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PSTOPO
0 0
Reserved
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
SMC_STOPCTRL field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–6
PSTOPO
Partial Stop Option
These bits control whether a Partial Stop mode is entered when STOPM=STOP. When entering a Partial
Stop mode from RUN mode, the PMC, SCG and flash remain fully powered, allowing the device to
wakeup almost instantaneously at the expense of higher power consumption. In PSTOP2, only system
clocks are gated allowing peripherals running on bus clock to remain fully functional. In PSTOP1, both
system and bus clocks are gated.
00 STOP - Normal Stop mode
01 PSTOP1 - Partial Stop with both system and bus clocks disabled
10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
11 Reserved
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
Reserved
This field is reserved.
This bit is reserved for future expansion. Software should write 0 to this bit to maintain compatibility.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
Chapter 25 System Mode Controller (SMC)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 571