NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 95 / 1325

6.5.3 Software interface
The programming model of the MMDVSQ is organized to be similar to the input
arguments passed to software libraries for integer divide and square root functions.
6.5.3.1 Operation activation and result retrieval
The MMDVSQ supports 2 mechanisms for initiating a divide operation:
• The default mechanism is a "fast start" where a write to the DSOR register begins the
divide.
• Alternatively, the start mechanism can begin after a write to the CSR register with
the CSR[SRT] set.
The CSR[DFS] indicator selects the divide start mechanism.
if CSR[DFS] = 0
then a divide is initiated by a write to the DSOR register
else a divide is initiated by a write to the CSR register with CSR[SRT] = 1
A square root calculation is initiated by a write to the RCND register.
For both divide and square root calculations, the result of the operation is retrieved by
reading the RES register. A memory read of this register while the calculation is still
being performed causes the access to be stalled via the insertion of bus wait states until
the new result is loaded into the register. Note a stalled bus cycle cannot be interrupted,
so if system interrupt latency is a concern, the processor should execute a simple wait
loop, for example, polling CSR[BUSY], before reading the RES register. This code
construct is fully interruptible, so interrupt latency is minimized.
6.5.3.2 Context save and restore
Given that multiple memory-mapped register accesses are needed for each divide and
square root calculation, interrupts may occur during the required sequence of operations.
As a result, the MMDVSQ’s programming model can be saved at entry to an interrupt
service routine (ISR) and then restored when redispatching to the interrupted task.
The module’s context can be saved by reading the DEND, DSOR, CSR, and RES
registers and storing them as part of the task state. There is one special consideration for
the task state save. If the last calculation was a zero divide and the divide-by-zero enable
is set (CSR[DZE] = 1), then a read of the RES register is error terminated. To avoid a
zero-divide error termination during a context save, the following sequence can be used:
1. Read DEND, DSOR, and CSR registers and save the values as part of the task state.
Chapter 6 Memory-Mapped Divide and Square Root (MMDVSQ)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 95