NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 236 / 1325

13.3.33 TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCDn_DLASTSGA)
Address: 4000_8000h base + 1018h (32d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLASTSGA
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset. •
DMA_TCDn_DLASTSGA field descriptions
Field Description
DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be
loaded into this channel (scatter/gather).
If (TCDn_CSR[ESG] = 0) then:
• Adjustment value added to the destination address at the completion of the major iteration count.
This value can apply to restore the destination address to the initial value or adjust the address to
reference the next data structure.
• This field uses two's complement notation for the final destination address adjustment.
Otherwise:
• This address points to the beginning of a 0-modulo-32-byte region containing the next transfer
control descriptor to be loaded into this channel. This channel reload is performed as the major
iteration count completes. The scatter/gather address must be 0-modulo-32-byte, otherwise a
configuration error is reported.
13.3.34 TCD Control and Status (DMA_TCDn_CSR)
Address: 4000_8000h base + 101Ch (32d × i), where i=0d to 7d
Bit 15 14 13 12 11 10 9 8
Read
BWC MAJORLINKCH
Write 0
Reset x* x* x* x* x* x* x* x*
Bit 7 6 5 4 3 2 1 0
Read
DONE
ACTIVE
MAJORELI
NK
ESG DREQ INTHALF INTMAJOR START
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset. •
Memory map/register definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
236 NXP Semiconductors