NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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42.5.6 LPTMR hardware trigger
The LPTMR hardware trigger asserts at the same time the CSR[TCF] is set and can be
used to trigger hardware events in other peripherals without software intervention. The
hardware trigger is always enabled.
When Then
The CMR is set to 0 with CSR[TFC] clear The LPTMR hardware trigger will assert on the first compare
and does not deassert.
The CMR is set to a nonzero value, or, if CSR[TFC] is set The LPTMR hardware trigger will assert on each compare
and deassert on the following increment of the CNR.
42.5.7 LPTMR interrupt
The LPTMR interrupt is generated whenever CSR[TIE] and CSR[TCF] are set.
CSR[TCF] is cleared by disabling the LPTMR or by writing a logic 1 to it.
CSR[TIE] can be altered and CSR[TCF] can be cleared while the LPTMR is enabled.
The LPTMR interrupt is generated asynchronously to the system clock and can be used to
generate a wakeup from any low-power mode, provided the LPTMR is enabled as a
wakeup source.
42.6 Usage Guide
LPTMR is very useful in low power situations. It can be used as a wake-up timer to wake
the MCU out of sleep modes after a certain amount of time. If used as pulse counter
mode with the glitch filter enabled, then there is no need for a clock to be on. The MCU
can wakeup based on counting pulses.
42.6.1 Time Counter mode
The typical usage of LPTMR is as Time Counter mode to generate periodic trigger pulses
and interrupts.
Example: LPTMR trigger a periodic interrupt every 1 second
• Enable the LPTMR module clock;
Usage Guide
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1064 NXP Semiconductors