NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Chapter 3
Core Overview
3.1 ARM Cortex-M0+
The ARM Cortex-M0+ is the member of the Cortex-M Series of processors targeting the
micro-controller market. It is an entry-level 32-bit processor designed for very cost
sensitive, low power applications. The Cortex-M0+ has a 2-stage pipeline von Neumann
architecture. The processor delivers exceptional energy efficiency through extensively
optimized design and provides high-end processing hardware including a single-cycle
multiplier. It also has an I/O port which supports single cycle loads and stores to tightly-
coupled peripherals (e.g. GPIO).
The Cortex-M0+ processor implements the ARMv6-M architecture, which is upward
compatible with other Cortex-M profile processors. It is based on the 16-bit Thumb
®
instruction set and includes Thumb-2 technology (including all but three 16-bit Thumb
opcodes plus seven 32-bit instructions). The Cortex-M0+ instruction set provides the
exceptional performance expected of a modern 32-bit architecture, with a higher code
density than 8-bit and 16-bit microcontrollers.
Cortex-M0+ Processor Features
• Thumb instruction set with Thumb-2 technology
• Nested Vectored Interrupt Controller (NVIC)
• Single-cycle 32-bit hardware multiplier
• Single-cycle I/O port
• Serial-Wire Debug port (SWD)
• Breakpoint & Watchpoint Units
• Micro Trace Buffer (MTB)
• 24-bit system tick timer (SysTick)
The detailed architecture and programming model of Cortex-M0+ processor are
discussed in the following documents from ARM.
• Cortex-M0+ Devices Generic User Guide
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 53