NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Table 39-20. Conditions for reload occurring at the next enabled reload point
When a new value was written Then
To the MOD register The MOD register is updated with its write buffer value.
To the HCR register The HCR register is updated with its write buffer value.
To the CNTIN register and CNTINC = 1 The CNTIN register is updated with its write buffer value.
To the C(n)V register and SYNCENm = 1 – where m indicates
the pair channels (n) and (n+1) The C(n)V register is updated with its write buffer value.
To the C(n+1)V register and SYNCENm = 1 – where m
indicates the pair channels (n) and (n+1) The C(n+1)V register is updated with its write buffer value.
NOTE
The reload points feature is independent of the PWM
synchronization.
At these reload points neither the channels outputs nor the FTM
counter are changed. Software must select these reload points at
the safe points in time.
39.5.30 Global Load
The global load mechanism allows several modules to have their double buffered
registers synchronously reloaded after a synchronization event if a write to one operation
is performed in the global load OK (GLDOK) bit in the FTM_PWMLOAD register.
Global load may be enabled or disabled configuring the global load enable (GLEN) bit in
the FTM_PWMLOAD register. Writing one in the GLDOK bit with GLEN enabled has
the same effect of writing one in the LDOK bit. Refer to SoC specific information about
global load connections.
Global load mechanism allows MOD, HCR, CNTIN, and C(n)V registers to be updated
with the content of the register buffer at configurable reload point. The figure below
shows an example of connection between FTM global load inputs and outputs
considering that GLDOK bit is implemented outside from FTM module.
Chapter 39 FlexTimer Module (FTM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 989