NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 601 / 1325

Note
The user must update the CMPH and CMPL registers prior to
enabling the EWM. After enabling the EWM, the counter resets
to zero, therefore the user shall provide a reasonable time after a
power-on reset for the external monitoring circuit to stabilize.
The user shall also ensure that the EWM_in pin is deasserted.
28.4.3 EWM Counter
It is an 8-bit ripple counter fed from a clock source that is independent of the peripheral
bus clock source. As the preferred time-out is between 1 ms and 100 ms the actual clock
source should be in the kHz range.
The counter is reset to zero after the CPU reset, or when EWM refresh action completes,
or at counter overflow. The counter value is not accessible to the CPU.
28.4.4 EWM Compare Registers
The compare registers CMPL and CMPH are write-once after a CPU reset and cannot be
modified until another CPU reset occurs.
The EWM compare registers are used to create a refresh window to refresh the EWM
module.
It is illegal to program CMPL and CMPH with same value. In this case, as soon as
counter reaches (CMPL + 1), EWM_out is asserted.
28.4.5 EWM Refresh Mechanism
Other than the initial configuration of the EWM, the CPU can only access the EWM by
the EWM Service Register. The CPU must access the EWM service register with correct
write of unique data within the windowed time frame as determined by the CMPL and
CMPH registers for correct EWM refresh operation. Therefore, three possible conditions
can occur:
Chapter 28 External Watchdog Monitor (EWM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 601