NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1109 / 1325

LPSPIx_TCR field descriptions (continued)
Field Description
0 The inactive state value of SCK is low.
1 The inactive state value of SCK is high.
30
CPHA
Clock Phase
This field is only updated between frames.
0 Data is captured on the leading edge of SCK and changed on the following edge.
1 Data is changed on the leading edge of SCK and captured on the following edge.
29–27
PRESCALE
Prescaler Value
Prescaler applied to the clock configuration register for all SPI bus transfers. This field is only updated
between frames.
000 Divide by 1.
001 Divide by 2.
010 Divide by 4.
011 Divide by 8.
100 Divide by 16.
101 Divide by 32.
110 Divide by 64.
111 Divide by 128.
26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
25–24
PCS
Peripheral Chip Select
Configures the peripheral chip select used for the transfer. This field is only updated between frames.
00 Transfer using LPSPI_PCS[0]
01 Transfer using LPSPI_PCS[1]
10 Transfer using LPSPI_PCS[2]
11 Transfer using LPSPI_PCS[3]
23
LSBF
LSB First
0 Data is transferred MSB first.
1 Data is transferred LSB first.
22
BYSW
Byte Swap
Byte swap will swap the contents of [31:24] with [7:0] and [23:16] with [15:8] for each transmit data word
read from the FIFO and each received data word stored to the FIFO (or compared with match registers).
0 Byte swap disabled.
1 Byte swap enabled.
21
CONT
Continuous Transfer
In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a
command word is received that starts a new frame.
In slave mode, when continuous transfer is enabled the LPSPI will only transmit the first FRAMESZ bits,
after which it will transmit received data assuming a 32-bit shift register.
Table continues on the next page...
Chapter 44 Low Power Serial Peripheral Interface (LPSPI)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1109