NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Table 8-3. Cycle definitions of decorated store: logical XOR
Pipeline Stage Cycle
x x+1 x+2
BME AHB_ap Forward addr to memory;
Decode decoration; Convert
master_wt to slave_rd;
Capture address, attributes Recirculate captured addr +
attr to memory as slave_wt <next>
BME AHB_dp <previous> Perform memory read; Form
(rdata ^ wdata) and capture
destination data in register Perform write sending
registered data to memory
8.4.1.4 Decorated store bit field insert (BFI)
This command inserts a bit field contained in the write data operand, defined by LSB
position (b) and the bit field width (w+1), into the memory "container" defined by the
access size associated with the store instruction using an atomic read-modify-write
sequence.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit)
or word (32-bit).
NOTE
For the word sized operation, the maximum bit field width is 16
bits. The core performs the required write data lane replication
on byte and halfword transfers.
The BFI operation can be used to insert a single bit into a peripheral. For this case, the w
field is simply set to 0, indicating a bit field width of 1.
iobfib
0 * 1 - -
mem_addr
iobfih
0 1 - b
mem_addr
iobfiw
0 1 b b mem_addr
*
*
* *
*
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
18
19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
b
b
b b
b
b b
b
b -
w
w w
w w
w
w w
w
w
w
Figure 8-6. Decorated address store: bit field insert
where addr[30:29] =10 for peripheral,addr[28] = 1 signals a BFI operation, addr[27:23] is
"b", the LSB identifier, addr[22:19] is "w", the bit field width minus 1 identifier, and
addr[18:0] specifies the address offset into the peripheral space based at 0x4000_0000 for
peripherals. The "-" indicates an address bit "don't care". Note, unlike the other decorated
store operations, BFI uses addr[19] as the least significant bit in the "w" specifier and not
as an address bit.
Chapter 8 Bit Manipulation Engine (BME)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 113