NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1260 / 1325

Table 47-11. I2S Master Configuration (continued)
Register Value Comments
TIMCFGn 0x0000_0202 Configure start bit, enable on trigger high
and never disable. Initial clock state is
logic 1.
TIMCTLn 0x01C3_0201 Configure dual 8-bit counter using Pin 2
output (bit clock), with Shifter 0 flag as
the inverted trigger. Set PINPOL to
invert the output shift clock.
TIMCMP(n+1) 0x0000_007F Configure 32-bit transfer with baud rate
of divide by 4 of the FlexIO clock. Set
TIMCMP[15:0] = (number of bits x baud
rate divider) - 1.
TIMCFG(n+1) 0x0000_0100 Enable when Timer 0 is enabled and
never disable.
TIMCTL(n+1) 0x0003_0383 Configure 16-bit counter using inverted
Pin 3 output (as frame sync).
SHIFTBUFn Data to transmit Transmit data can be written to
SHIFTBUFBIS, use the Shifter Status
Flag to indicate when data can be
written using interrupt or DMA request.
Can support LSB first transfer by writing
to SHIFTBUF register instead.
SHIFTBUF(n+1) Data to receive Received data can be read from
SHIFTBUFBIS, use the Shifter Status
Flag to indicate when data can be read
using interrupt or DMA request. Can
support LSB first transfer by reading
from SHIFTBUF register instead.
47.5.7 I2S Slave
I2S slave mode can be supported using two Timers, two Shifters and four Pins (for single
transmit and single receive, other combinations of transmit and receive are possible).
The transmit data must be written to the transmit buffer register before the external frame
sync asserts, otherwise the shifter error flag will be set.
Due to synchronization delays, the output valid time for the serial output data is 2.5
FlexIO clock cycles, so the maximum baud rate is divide by 6 of the FlexIO clock
frequency.
The output valid time of I2S slave is max 2.5 cycles because there is a maximum 1.5
cycle delay on the clock synchronization plus 1 cycle to output the data
Application Information
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1260 NXP Semiconductors