41.3.2 PWTIN[3:0] — pulse width timer capture inputs
The input signals are pulse capture inputs which can come from internal or external. The
PWT input is selected by PINSEL[1:0] to be routed to the pulse width timer. If the input
comes from external and is selected as the PWT input, the input port is enabled for PWT
function by PINSEL[1:0] automatically. The minimum pulse width to be measured is 1
PWTCLK cycle, any pulse narrower than this value is ignored by PWT module. The
PWTCLK cycle time depends on the PWT clock source selection and pre-scaler rate
setting.
41.3.3 ALTCLK— alternative clock source for counter
The PWT has an alternative clock input ALTCLK which can be selected as the clock
source of the counter when the PCLKS bit is set. The ALTCLK input must be
synchronized by the bus clock. Variations in duty cycle and clock jitter must also be
accommodated so that the ALTCLK signal must not exceed one-fourth of the bus
frequency. The ALTCLK pin can be shared with a general-purpose port pin. See the Pins
and Connections chapter for the pin location and priority of this function.
Memory Map and Register Descriptions
PWT memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4005_6000 Pulse Width Timer Control and Status Register (PWT_CS)
8
R/W
00h
4005_6001 Pulse Width Timer Control Register (PWT_CR)
8
R/W
00h
4005_6002
Pulse Width Timer Positive Pulse Width Register: High
(PWT_PPH)
8
R
00h
4005_6003
Pulse Width Timer Positive Pulse Width Register: Loq
(PWT_PPL)
8
R
00h
4005_6004
Pulse Width Timer Negative Pulse Width Register: High
(PWT_NPH)
8
R
00h
4005_6005
Pulse Width Timer Negative Pulse Width Register: Low
(PWT_NPL)
8
R
00h
4005_6006 Pulse Width Timer Counter Register: High (PWT_CNTH)
8
R
00h
4005_6007 Pulse Width Timer Counter Register: Low (PWT_CNTL)
8
R
00h
41.4
Memory Map and Register Descriptions
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1036
NXP Semiconductors
Summary of Contents for Kinetis KE1xZ256
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