NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1041 / 1325

41.4.7 Pulse Width Timer Counter Register: High (PWT_CNTH)
Address: 4005_6000h base + 6h offset = 4005_6006h
Bit 7 6 5 4 3 2 1 0
Read PWTH
Write
Reset 0 0 0 0 0 0 0 0
PWT_CNTH field descriptions
Field Description
PWTH PWT counter[15:8]
High byte of PWT counter register.
41.4.8 Pulse Width Timer Counter Register: Low (PWT_CNTL)
Address: 4005_6000h base + 7h offset = 4005_6007h
Bit 7 6 5 4 3 2 1 0
Read PWTL
Write
Reset 0 0 0 0 0 0 0 0
PWT_CNTL field descriptions
Field Description
PWTL PWT counter[7:0]
Low byte of PWT counter register.
Functional description
41.5.1 PWT counter and PWT clock pre-scaler
The pulse width timer (PWT) measures duration of a pulse or the period of a signal input
to the PWTIN by a 16-bit free running counter (PWT_CNTH:L). There is a clock pre-
scaler (CLKPRE) in PWT module that provides the frequency divided clock to the
PWT_CNTH:L.. The clock pre-scaler can select clock input from bus clock and
alternative clock by PWT_CR[PCLKS].
41.5
Chapter 41 Pulse Width Timer (PWT)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1041