NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1212 / 1325

Table 46-3. Receiver Wakeup Options (continued)
RWU MA1 | MA2 MATCFG WAKE:RWUID Receiver Wakeup
1 0 00 10 Receiver wakeup on
address mark
1 1 11 X0 Receiver wakeup on
data match
0 1 00 X0 Address mark address
match, IDLE flag not set
for discarded
characters
0 1 00 X1 Address mark address
match, IDLE flag set for
discarded characters
0 1 01 X0 Idle line address match
0 1 10 X0 Address match on and
address match off,
IDLE flag not set for
discarded characters
0 1 10 X1 Address match on and
address match off,
IDLE flag set for
discarded characters
46.4.3.2.1 Idle-line wakeup
When wake is cleared, the receiver is configured for idle-line wakeup. In this mode,
LPUART_CTRL[RWU] is cleared automatically when the receiver detects a full
character time of the idle-line level. The LPUART_CTRL[M], LPUART_CTRL[M7]
and LPUART_BAUD[M10] control bit selects 7-bit to 10-bit data mode and the
LPUART_BAUD[SBNS] bit selects 1-bit or 2-bit stop bit number that determines how
many bit times of idle are needed to constitute a full character time, 9 to 13 bit times
because of the start and stop bits.
When LPUART_CTRL[RWU] is one and LPUART_STAT[RWUID] is zero, the idle
condition that wakes up the receiver does not set the LPUART_STAT[IDLE] flag. The
receiver wakes up and waits for the first data character of the next message that sets the
LPUART_STAT[RDRF] flag and generates an interrupt if enabled. When
LPUART_STAT[RWUID] is one, any idle condition sets the LPUART_STAT[IDLE]
flag and generates an interrupt if enabled, regardless of whether LPUART_CTRL[RWU]
is zero or one.
The idle-line type (LPUART_CTRL[ILT]) control bit selects one of two ways to detect
an idle line. When LPUART_CTRL[ILT] is cleared, the idle bit counter starts after the
start bit so the stop bit and any logic 1s at the end of a character count toward the full
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1212 NXP Semiconductors