NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1201 / 1325

Field Function
TXCTSC Configures if the CTS state is checked at the start of each character or only when the transmitter is idle.
0 - CTS input is sampled at the start of each character.
1 - CTS input is sampled when the transmitter is idle.
3
RXRTSE
Receiver request-to-send enable
Allows the RTS output to control the CTS input of the transmitting device to prevent receiver overrun.
NOTE: Do not set both RXRTSE and TXRTSE.
0 - The receiver has no effect on RTS.
1 - RTS is deasserted if the receiver data register is full or a start bit has been detected that would
cause the receiver data register to become full. RTS is asserted if the receiver data register is not
full and has not detected a start bit that would cause the receiver data register to become full.
2
TXRTSPOL
Transmitter request-to-send polarity
Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the polarity of the receiver RTS.
RTS will remain negated in the active low state unless TXRTSE is set.
0 - Transmitter RTS is active low.
1 - Transmitter RTS is active high.
1
TXRTSE
Transmitter request-to-send enable
Controls RTS before and after a transmission.
0 - The transmitter has no effect on RTS.
1 - When a character is placed into an empty transmitter data buffer , RTS asserts one bit time
before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter
data buffer and shift register are completely sent, including the last stop bit.
0
TXCTSE
Transmitter clear-to-send enable
TXCTSE controls the operation of the transmitter. TXCTSE can be set independently from the state of
TXRTSE and RXRTSE.
0 - CTS has no effect on the transmitter.
1 - Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready
to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD
remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a
character is being sent do not affect its transmission.
46.3.1.12 LPUART FIFO (FIFO)
46.3.1.12.1 Address
Register Offset
FIFO Base a 28h offset
46.3.1.12.2 Function
This register provides the ability for the programmer to turn on and off FIFO
functionality. It also provides the size of the FIFO that has been implemented. This
register may be read at any time. This register must be written only when CTRL[RE] and
CTRL[TE] are cleared/not set and when the data buffer/FIFO is empty.
Chapter 46 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1201