NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 270 / 1325

14.3 SRAM memory
14.3.1 SRAM sizes
This device contains SRAM accessed by bus masters through the cross-bar switch. The
on-chip SRAM is split into SRAM_L and SRAM_U regions where the SRAM_L and
SRAM_U ranges form a contiguous block in the memory map anchored at address
0x2000_0000. As such:
• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending
address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning
address.
NOTE
Burst-access cannot occur across the 0x2000_0000 boundary
that separates the two SRAM arrays. The two arrays should be
treated as separate memory ranges for burst accesses.
The amount of SRAM for the devices covered in this document is shown in the following
table.
Device SRAM_L size
(KB)
SRAM_U size
(KB)
Total SRAM (KB) Address Range
MKE1xZ256Vxx7 8 24 32 0x1FFF_E000-0x2000_5FFF
MKE1xZ128Vxx7 4 12 16 0x1FFF_F000-0x2000_2FFF
14.3.2 SRAM retention in low power modes
The SRAM is retained power on to all power modes on this device.
14.4 System memory map
The following table shows the high-level device memory map. This map provides the
complete architectural address space definition for the various sections. Based on the
physical sizes of the memories and peripherals, the actual address regions used may be
smaller.
SRAM memory
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
270 NXP Semiconductors