NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 401 / 1325

SCG_LPFLLTCFG field descriptions (continued)
Field Description
Use to divide the reference clock down for LPFLL trimming by 1,2,3,4…..31,32. The divided frequency
should be either 32.768 KHz or 2 MHz.
00000 Divide by 1
00001 Divide by 2
00010 Divide by 3
....
11110 Divide by 31
11111 Divide by 32
7–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
TRIMSRC Trim Source
Configures the reference clock source to tune the LPFLL.
00 SIRC
01 FIRC
10 System OSC
11 RTC OSC
18.3.22 Low Power FLL Status Register (SCG_LPFLLSTAT)
This register is loaded from IFR during reset. These register gets uploaded with the trim
values generated by LPFLL auto trimming which is enabled when LPFLL is enabled and
LPFLLTREN=1 and LPFLLTRUP=1. When LPFLL auto trimming is enabled and
LPFLLTRUP is off, writes to this register is allowed and values written to this register
are used to trim LPFLL clock.
Address: 4006_4000h base + 514h offset = 4006_4514h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
AUTOTRIM
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * * *
* Notes:
AUTOTRIM field: Reset values are loaded out of IFR. •
SCG_LPFLLSTAT field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
AUTOTRIM Auto Tune Trim Status
Table continues on the next page...
Chapter 18 System Clock Generator (SCG)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 401