NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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the protocol of the AMBA-AHB system bus interfaces. The PBRIDGE module converts
the AHB system bus protocol into the IPS/APB protocol used by the attached slave
peripherals.
8.2.2 Features
The key features of the BME include:
• Lightweight implementation of decorated storage for selected address spaces
• Additional access semantics encoded into the reference address
• Resides between a switch slave port and a peripheral bridge bus controller
• Two-stage pipeline design matching the AHB system bus protocol
• Combinationally passes non-decorated accesses to peripheral bridge bus controller
• Conversion of decorated loads and stores from processor core into atomic read-
modify-writes
• Decorated loads support unsigned bit field extracts, load-and-{set,clear} 1-bit
operations
• Decorated stores support bit field inserts, logical AND, OR, and XOR operations
• Support for byte, halfword and word-sized decorated operations
• Supports minimum signal toggling on AHB output bus to reduce power dissipation
8.2.3 Modes of operation
The BME module does not support any special modes of operation. As a memory-
mapped device located on a crossbar slave AHB system bus port, BME responds strictly
on the basis of memory addresses for accesses to the peripheral bridge bus controller.
All functionality associated with the BME module resides in the core platform's clock
domain; this includes its connections with the crossbar slave port and the PBRIDGE bus
controller.
8.3 Memory map and register definition
The BME module provides a memory-mapped capability and does not include any
programming model registers.
The exact set of functions supported by the BME are detailed in the Functional
description .
Chapter 8 Bit Manipulation Engine (BME)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 107