NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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The peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000
plus a 4 KB space based at 0x400F_F000 for GPIO accesses; the decorated address space
is mapped to the 448 MB region located at 0x4400_0000–0x5FFF_FFFF.
8.4 Functional description
Information found here details the specific functions supported by the BME.
Recall the combination of the basic load and store instructions of the Cortex-M
instruction set architecture (v6M, v7M) plus the concept of decorated storage provided by
the BME, the resulting implementation provides a robust and efficient read-modify-write
capability to this class of ultra low-end microcontrollers. The resulting architectural
capability defined by this core platform function is targeted at the manipulation of n-bit
fields in peripheral registers and is consistent with I/O hardware addressing in the
Embedded C standard. For most BME commands, a single core read or write bus cycle is
converted into an atomic read-modify-write, that is, an indivisible "read followed by a
write" bus sequence.
Consider decorated store operations first, then decorated loads.
8.4.1 BME decorated stores
The functions supported by the BME's decorated stores include three logical operators
(AND, OR, XOR) plus a bit field insert.
For all these operations, BME converts a single decorated AHB store transaction into a 2-
cycle atomic read-modify-write sequence, where the combined read-modify operation is
performed in the first AHB data phase, and then the write is performed in the second
AHB data phase.
A generic timing diagram of a decorated store showing a peripheral bit field insert
operation is shown as follows:
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
108 NXP Semiconductors