NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1039 / 1325

PWT_CR field descriptions (continued)
Field Description
0 The selected PWTIN hasn’t changed its original states from last time.
1 The selected PWTIN has toggled its states.
3
LVL
PWTIN Level when Overflows
This Read Only bit signalizes the selected PWTIN states when the coutner overflows to read out.
PRE PWT Clock Prescaler (CLKPRE) Setting
Selects the value by which the clock is divided to clock the PWT counter.
000 Clock divided by 1.
001 Clock divided by 2.
010 Clock divided by 4.
011 Clock divided by 8.
100 Clock divided by 16.
101 Clock divided by 32.
110 Clock divided by 64.
111 Clock divided by 128.
41.4.3 Pulse Width Timer Positive Pulse Width Register: High
(PWT_PPH)
Address: 4005_6000h base + 2h offset = 4005_6002h
Bit 7 6 5 4 3 2 1 0
Read PPWH
Write
Reset
0 0 0 0 0 0 0 0
PWT_PPH field descriptions
Field Description
PPWH Positive Pulse Width[15:8]
High byte of captured positive pulse width value.
41.4.4 Pulse Width Timer Positive Pulse Width Register: Loq
(PWT_PPL)
Address: 4005_6000h base + 3h offset = 4005_6003h
Bit 7 6 5 4 3 2 1 0
Read PPWL
Write
Reset
0 0 0 0 0 0 0 0
Chapter 41 Pulse Width Timer (PWT)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1039