NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Table 37-4. Comparator sample/filter maximum latencies
Mode #
C0[E
N]
C0[W
E]
C0[S
E]
C0[FILTER_
CNT]
Co[FPR] Operation Maximum latency
1
1 0 X X X X Disabled N/A
2A 1 0 0 0x00 X Continuous Mode T
PD
2B 1 0 0 X 0x00
3A 1 0 1 0x01 X Sampled, Non-Filtered mode T
PD
+ T
SAMPLE
+ T
per
3B 1 0 0 0x01 > 0x00 T
PD
+ (C0[FPR] * T
per
) + T
per
4A 1 0 1 > 0x01 X Sampled, Filtered mode T
PD
+ (C0[FILTER_CNT] *
T
SAMPLE
) + T
per
4B 1 0 0 > 0x01 > 0x00 T
PD
+ (C0[FILTER_CNT] *
C0[FPR] x T
per
) + T
per
5A 1 1 0 0x00 X Windowed mode T
PD
+ T
per
5B 1 1 0 X 0x00 T
PD
+ T
per
6 1 1 0 0x01 0x01 - 0xFF Windowed / Resampled
mode
T
PD
+ (C0[FPR] * T
per
) +
2T
per
7 1 1 0 > 0x01 0x01 - 0xFF Windowed / Filtered mode T
PD
+ (C0[FILTER_CNT] *
C0[FPR] x T
per
) + 2T
per
1. T
PD
represents the intrinsic delay of the analog component plus the polarity select logic. T
SAMPLE
is the clock period of the
external sample clock. T
per
is the period of the bus clock.
37.10 Interrupts
The CMP module is capable of generating an interrupt on either the rising- or falling-
edge of the comparator output, or both. Assuming the CMP DMA enable bit is not set,
the following table gives the conditions in which the interrupt request is asserted and
deasserted.
Table 37-5. CMP interrupt generations
When Then
C0[IER] and C0[CFR] are set The interrupt request is asserted
C0[IEF] and C0[CFF] are set The interrupt request is asserted
C0[IER] and C0[CFR] are cleared for a rising-edge interrupt The interrupt request is deasserted
C0[IEF] and C0[CFF] are cleared for a falling-edge interrupt The interrupt request is deasserted
Chapter 37 Comparator (CMP)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 811