NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 91 / 1325

6.5.1.1.3 Special case: Divide-by-Zero
For both signed and unsigned divides, if the divisor is zero, the MMDVSQ hardware
detects this condition and the CSR[DZ] indicator set. The quotient result is forced to
0x0000_0000. If the remainder is selected as the output of this calculation, it also returns
0x0000_0000. Additionally, if CSR[DZE] = 1, then an attempted read of the Result
register (RES) is error terminated to provide a simple mechanism to signal software of
the divide-by-zero condition.
Integer square root
6.5.1.2.1 Overview
The unsigned square root algorithm begins by creating a 32-bit “one-hot” bit vector
signaling the highest power of four of the contents of the Radicand register (RCND). It
then iterates through an algorithm involving magnitude comparisons of the RCND
register versus the working result plus bit vector summation, conditional decrementing of
the radicand, a 1-bit right shift of the result, and a 2-bit right shift of the one-hot bit
vector.
Processing two bits of the radicand per cycle, the result register finishes with the integer
portion of the square root calculation. The module includes early termination logic so that
the execution time is data dependent, based on the magnitude of the input radicand. See
Table 6-5 for more execution time details. Since both algorithms share common hardware
structures, the incremental cost of the square root logic is an extremely small delta to the
basic divide hardware.
The square root algorithm was exhaustively compared (that is, all 2
32
possible input
values) against the standard GNU C library implementation, which converts the unsigned
integer input into a double-precision floating-point number, calculates the double-
precision square root and then converts it back into an unsigned integer. Each input value
calculated identical square root results.
6.5.1.2.2 Square root using Q notation
Consider the use of Q notation for square root calculations returning fractional values.
The following description is taken from
http://en.wikipedia.org/wiki/Q_(number_format) .
6.5.1.2
Chapter 6 Memory-Mapped Divide and Square Root (MMDVSQ)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 91