NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 924 / 1325

39.5.7 Edge-Aligned PWM (EPWM) mode
The Edge-Aligned mode is selected when:
• QUADEN = 0
• DECAPEN = 0
• COMBINE = 0
• CPWMS = 0, and
• MSB = 1
The EPWM period is determined by (MOD − CNTIN + 0x0001) and the pulse width
(duty cycle) is determined by (CnV − CNTIN).
The CHF bit is set and the channel (n) interrupt is generated if CHIE = 1 at the channel
(n) match (FTM counter = CnV), that is, at the end of the pulse width.
This type of PWM signal is called edge-aligned because the leading edges of all PWM
signals are aligned with the beginning of the period, which is the same for all channels
within an FTM.
period
counter overflow counter overflow counter overflow
channel (n) output
channel (n) match channel (n) match channel (n) match
pulse
width
Figure 39-20. EPWM period and pulse width with ELSB:ELSA = 1:0
If (ELSB:ELSA = 0:0) when the counter reaches the value in the CnV register, the CHF
bit is set and the channel (n) interrupt is generated if CHIE = 1, however the channel (n)
output is not controlled by FTM.
If (ELSB:ELSA = 1:0), then the channel (n) output is forced high at the counter overflow
when the CNTIN register value is loaded into the FTM counter, and it is forced low at the
channel (n) match (FTM counter = CnV). See the following figure.
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
924 NXP Semiconductors