NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 961 / 1325

39.5.17 Fault control
The fault control is enabled if (FAULTM[1:0] ≠ 0:0).
FTM can have up to four fault inputs. FAULTnEN bit (where n = 0, 1, 2, 3) enables the
fault input n and FFLTRnEN bit enables the fault input n filter. FFVAL[3:0] bits select
the value of the enabled filter in each enabled fault input.
First, each fault input signal is synchronized by the FTM input clock; see the
synchronizer block in the following figure. Following synchronization, the fault input n
signal enters the filter block. When there is a state change in the fault input n signal, the
5-bit counter is reset and starts counting up. As long as the new state is stable on the fault
input n, the counter continues to increment. If the 5-bit counter overflows, that is, the
counter exceeds the value of the FFVAL[3:0] bits, the new fault input n value is
validated. It is then transmitted as a pulse edge to the edge detector.
If the opposite edge appears on the fault input n signal before validation (counter
overflow), the counter is reset. At the next input transition, the counter starts counting
again. Any pulse that is shorter than the minimum value selected by FFVAL[3:0] bits (×
system clock) is regarded as a glitch and is not passed on to the edge detector.
The fault input n filter is disabled when the FFVAL[3:0] bits are zero or when
FAULTnEN = 0. In this case, the fault input n signal is delayed 2 rising edges of the
FTM input clock and the FAULTFn bit is set on 3th rising edge of the FTM input clock
after a rising edge occurs on the fault input n.
If FFVAL[3:0] ≠ 0000 and FAULTnEN = 1, then the fault input n signal is delayed (3 +
FFVAL[3:0]) rising edges of the FTM input clock, that is, the FAULTFn bit is set (4 +
FFVAL[3:0]) rising edges of the FTM input clock after a rising edge occurs on the fault
input n.
fault input n*
* where n = 3, 2, 1, 0
synchronizer fault input n* value
FAULTFn*
0000)
and (FFLTRnEN*)
0
1
rising edge
detector
fault input
polarity
control
Fault filter
(5-bit counter)
CLK CLK
D D Q Q
FLTnPOL
(FFVAL[3:0]
FTM input clock
Figure 39-73. Fault input n control block diagram
Chapter 39 FlexTimer Module (FTM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 961