NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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DMA_TCDn_CSR field descriptions
Field Description
15–14
BWC
Bandwidth Control
Throttles the amount of bus bandwidth consumed by the eDMA. Generally, as the eDMA processes the
minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field
forces the eDMA to stall after the completion of each read/write access to control the bus request
bandwidth seen by the crossbar switch.
00 No eDMA engine stalls.
01 Reserved
10 eDMA engine stalls for 4 cycles after each R/W.
11 eDMA engine stalls for 8 cycles after each R/W.
13–11
Reserved
This field is reserved.
10–8
MAJORLINKCH
Major Loop Link Channel Number
If (MAJORELINK = 0) then:
• No channel-to-channel linking, or chaining, is performed after the major loop counter is exhausted.
Otherwise:
• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at
the channel defined by this field by setting that channel’s TCDn_CSR[START] bit.
7
DONE
Channel Done
This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count
reaches zero. The software clears it, or the hardware when the channel is activated.
The access of this field is W0C, write-zero-to-clear.
NOTE: This bit must be cleared to write the MAJORELINK or ESG bits.
6
ACTIVE
Channel Active
This flag signals the channel is currently in execution. It is set when channel service begins, and is cleared
by the eDMA as the minor loop completes or when any error condition is detected.
5
MAJORELINK
Enable channel-to-channel linking on major loop complete
As the channel completes the major loop, this flag enables the linking to another channel, defined by
MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism that
sets the TCDn_CSR[START] bit of the specified channel.
NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while
the TCDn_CSR[DONE] bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
4
ESG
Enable Scatter/Gather Processing
As the channel completes the major loop, this flag enables scatter/gather processing in the current
channel. If enabled, the eDMA engine uses DLASTSGA as a memory pointer to a 0-modulo-32 address
containing a 32-byte data structure loaded as the transfer control descriptor into the local memory.
NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written
to while the TCDn_CSR[DONE] bit is set.
Table continues on the next page...
Chapter 13 Enhanced Direct Memory Access (eDMA)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 237