NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 362 / 1325

Table 17-1. Peripheral Clock Summary (continued)
Module Name Bus Interface
Clock Gating
Peripheral Functional Clock Max Frequency of Clock
Source
Gated by [CGC]
bit of PCC
Clocks controlled
by [PCS] bits of
PCC
1
Clocks controlled by
registers inside
module
DMA Yes SYS_CLK Max: SYS_CLK
Memory Modules
FTFE Yes FLASH_CLK Max: FLASH_CLK
SYS RAM No SYS_CLK Max: SYS_CLK
Analog Modules
ADC0–ADC1 Yes FIRC_CLK,
SIRC_CLK,
FLL_CLK,
SOSC_CLK - Max: 50 MHz
ACMP0–ACMP1 Yes BUS_CLK Max: BUS_CLK
TSI Yes BUS_CLK Max: BUS_CLK
1. The clock sources undergo clock divider DIV x in SCG (output to PCC). For details, see the "High-Level clocking diagram"
section in Clocking chapter and the "Chip-specific information" section in each module chapter.
17.6.1 LPO clock distribution
PMC
LPO128K
÷128
1 kHz
128 kHz
WDOG
EWM
LPTMR
RTC
PORT Control
17.6.2 EWM clocks
This table shows the EWM clocks and the corresponding chip clocks.
Table 17-2. EWM clock connections
Module clock Chip clock
Low Power Clock 128 kHz LPO Clock (LPO_CLK)
Module clocks
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
362 NXP Semiconductors